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Outcome

High-level synthesis implementation of an embedded real-time HEVC intra encoder on FPGA for media applications

Author: Panu Sjövall, Ari Lemmetti, Jarno Vanne, Sakari Lahti, Timo D. Hämäläinen

Title: High-level synthesis implementation of an embedded real-time HEVC intra encoder on FPGA for media applications

Lead Beneficiary: TAU

Published: 2022

Place of publication: ACM Transactions on Design Automation of Electronic Systems

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Acknowledgement

ADACORSA has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 876019.
The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Germany, Netherlands, Austria, France, Sweden, Cyprus, Greece, Lithuania, Portugal, Italy, Finland, Turkey.