--> --> --> -->

   

  

 

 

 

Outcome

High-level synthesis implementation of an accurate HEVC interpolation filter on an FPGA

Author: Panu Sjövall, Matti Rasinen, Ari Lemmetti, Jarno Vanne

Title: High-level synthesis implementation of an accurate HEVC interpolation filter on an FPGA

Lead Beneficiary: TAU

Published: 2021

Place of publication: The IEEE Nordic Circuits and Systems Conference (NorCAS)

Download

  

 

Acknowledgement

ADACORSA has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 876019.
The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Germany, Netherlands, Austria, France, Sweden, Cyprus, Greece, Lithuania, Portugal, Italy, Finland, Turkey.